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The Metal-Oxide-Semiconductor interface is one of the most basic element of today's microelectronic devices. It is fundamental to understand its basic properties to investigate integrated circuits. The example describes a simple MOS capacitor Capacitance-Voltage behavior, and focuses on its most known regions. Dedicated theoretical background can be found in \citep{sze2006physics}


It is built up from $Si(p+)|SiO_2|Si(n)$ layers as depicted in figure 1. The left contact, the highly p-doped Si layer is used as a metal contact.


Figure 1. Band-structure at zero bias

The influence of the strain to the band-structure is not considered, and the bandgap of the $SiO_2$ layer was chosen to be arbitrary high 1). As it is shown in figure 1, that the screening length in the p type layer is much longer then in the n type layer due the lower doping.

Voltage characteristics

If we apply bias to the structure there is no current flow due the lack of charge carriers in the oxide. The Fermi-levels are flat in the doped regions. We can separate the voltage characteristics of the structure in three regions: accumulation, depletion, inversion


The density of electrons in the n doped layer changes linearly with the applied bias. The resulted charge density distribution is depicted in ref 2. It shows that the concentration of majority type charge carriers(holes) in the p doped layer is higher at the interface, than in bulk. $\rightarrow$ Accumulation.


As the bias voltage gets lower the density of holes in the substrate gets lower, and the density of the electrons gets higher. After a certain point (flat-band condition) the two densities become equal $\rightarrow$ Depletion. Close to the flat band condition the densities are plotted in figure 3.


For even lower negative bias voltage the concentration of electrons in the $p$ type layer gets more than the density of holes $\rightarrow$ Inversion, which is depicted in figure 4.


Figure 2. Accumulation


Figure 3. Depletion


Figure 4. Inversion

Capacitance relation

As the accumulated charge strongly depends on the applied bias, one can calculate the differential capacitance of the structure: \begin{equation} C = \frac{\partial Q}{\partial U} \end{equation}

Plotting the calculated $Q$ in the n type region, with derivation one gets the capacitance, which is plotted in figure 5.


Figure 5. Capacitance diagram

1) As long as there is no current flow the fermi-levels in the doped Si layers remain flat, and the voltage drop is at the oxide.
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