Junction Gate FET

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Among different Field effect transistor types the JFET might be the oldest one. In this simple example we are going to simulate a basic structure in two-dimensions.



Figure 1. Structure of the simulated double gate n-channel JFET

The simulated structure is schematically drawn in figure \ref{fig:structure}. It is buit from Si, and the channel doping was chosen do be $1E24\frac{1}{m^3}$, while the highly doped gate region has $1E25\frac{1}{m^3}$ acceptor density.

Properties at zero bias

If there is no applied bias on the gate or the drain contacts, the structure shows the basic properties of a p-n junction between the gate and the channel contacts. It creates a depletion region between the p and n doped parts, which size can be controlled by the gate voltage.


Figure 2. Band profile x-axis slice


Figure 3. Band profile y-axis slice

The electron density is plotted in figure 4., which shows that the electron density in the channel region is low resulting that the FET is in off state.

	%\draw [draw=white,fill=white] (0,0) rectangle (1,1);
        \node[inner sep=0pt] (russell) at (0,0)
	\draw [dashed] (0,-0.5) ellipse (2 and 0.3);
	\draw [dashed] (0, -0.8)  to[out=10,in=90] (-2, -2) node[align=right, below] {Channel region};	
	\draw [draw = black] (-1,-1.71) rectangle (1,-1.21);
	\draw [draw = black] (-1,0.19) rectangle (1,0.69);
	\draw [dashed] (1, -1.46) to[out=-0,in=90] (4, -2) node[align=right, below] {Gate};	
	\draw [dashed] (1, 0.44) to[out=-0,in=90] (4, -2);	

	%	\draw [|->] (0, 0) --(0, 3);
	%	\draw [draw=white,fill=white] (0,-2) rectangle (1,-0.1);	

Figure 4. Electron density at zero bias

Electrical properties

If we apply bias between the source and drain regions electron current starts to flow, which is limited by the electron density in the channel region. \footnote{The drop of the fermi-level happens at the channel}. If we change the gate bias voltage we change the electron density in the channel region, which lets higher current flow in the device. The gate voltage characteristics is plotted in figure 5.

After a certain point the conducting channel region for rising source-drain voltage starts to get narrower, resulting a limitation of the current. In our simulation it shows the the gradient of the U-I curve changes after a certain bias voltage in figure 6.


Figure 5. Drain-Source voltage characteristics


Figure 6. Gate-Source characteristics
  • physicswiki/semiconductors/jfet/jfet.txt
  • Last modified: 2019/04/09 12:20
  • by zoltan.jehn