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The most basic active part of today's microelectronics devices is the MOSFET transistor. The larger devices with longer channel length can be simulated with classical semiconductor device equations. But as the channel length becomes smaller and reaches the several times 10 nm-s length the proposed model loses its validity.


The schematics of the simulated structure is depicted in figure 2. It is built on silicon with the parameters summarized in table 1. - the metal gate material is simplified with highly n-doped Si material. The detailed dimensions and geometry can be found in the project online.


Figure 1. Structure of the N-channel MOSFET

	Channel length	& 850 nm  \\
	Oxide height	& 20 nm  \\
	Substrate doping	& 5E23 $\frac{1}{m^3}$  \\
	Gate doping & 1E25 $\frac{1}{m^3}$\\
	Source/Drain doping & 5E23 $\frac{1}{m^3}$

Table 1. Parameters of the simulated FET

Bandstructure at zero bias

The conduction-band profile of the structure is plotted in figure 2. When the bias is zero, the electron concentration in the channel region is low, which reflects that the resistance of the device is high between the source and drain contacts.


Figure 2. Conduction band profile at zero bias.

At zero voltage the conduction band profile is depicted in figure 2.The MOS channel and the two pn-junction can be observed at the source and drain regions. In figure 3. the y-slice of the conduction band is plotted, which depicts the MOS band structure in 1D. While in figure 4. the horizontal slice is plotted which is the potential barrier that should be lowered to make the MOSFET conduct.


Figure 3. Conduction band profile y-axis slice.


Figure 4. Conduction band profile x-axis slice.

Voltage Characteristics

The theoretical voltage characteristics can be reproduced with our simulation. In figure 5. the simple drain-source current is plotted in the function of the drain-source voltage, for various gate-source voltage. It shows the pinch-off effect, and follows the exponential rule for the saturation current plotted in figure 6..


Figure 5. DS current in the structure for various gate voltages.


Figure 6. DS current for various GS voltages for fixed U$_{DS}=0.2V$
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